1. Field of the Invention
The invention relates generally to electronic processing arrangements in a data acquisition system. More particularly, it relates to a method for reducing overall power in a data acquisition system. The present invention has use especially, but not exclusively, in the field of seismic sensing applications where it is desired to achieve significant power savings.
2. Description of the Prior Art
As is generally known in the art, a typical data acquisition system 100 comprises a PGA (programmable gain amplifier) block 102, an ADC (analog-to-digital converter) block 104, and a decimation filter block 106, as shown in FIG. 1 and labeled as “Prior Art.” The system 100 may be used for converting an analog input signal of a signal source (seismic sensor or transducer) to a digital output signal. Specifically, the analog input signal is applied through input terminals 108, 110 to the PGA block 102 which, in turn, produces an amplified signal on its output lines 112, 114. The output lines 112, 114 from the PGA block 102 are coupled to the input of the ADC block 104 which generates a digitized signal on its output lines 116, 118. The digitized signal is passed to the decimation filter block 106 which produces the filtered digital output signal on output terminals 120, 122. The gain of the PGA block 102 is controlled by gain control signals at gain control lines 124-128. Since the input terminals 108, 110 may receive different input signals each having different voltage characteristics, the amount of amplification required to be provided by the amplifier block 102 can be adjusted via the signals applied at gain control lines 124-128 depending upon the signal level applied to the input terminals 108, 110.
In seismic applications, the dynamic range, power consumption and linearity of the PGA block 102 are critical parameters. Further, power conservation is a high priority since any power savings achieved will result in significant reduced cost for systems used for conducting seismic exploration. The total noise power of a channel in the digital acquisition system 100 is given by the sum (in RMS sense) of the noise power of the amplifier block 102 and the noise power of the ADC block 104. Depending upon the gain setting of PGA, the use of the PGA block 102 will reduce the ADC block's noise when that noise is input-referred to the PGA block's input. As defined herein, the “input-referred” noise at the input of the PGA block 102 means the noise of the ADC block 104 divided by the gain of the PGA block. The PGA block 102 is typically designed and rated for its input-referred noise. As the gain of the amplifier block 102 is increased, the noise at its output on lines 112, 114 will also be increased. Accordingly, at a lower gain setting of the PGA block 102, the contribution of the noise power from the amplifier will be invariably small when compared to the noise power from the ADC block 104, as the ADC block 104 may have a relatively high noise power.
However, the use of the PGA block 102 in the data acquisition system 100 of FIG. 1 suffers from a drawback of being power inefficient since there is no control of the power in either the amplifier block 102 and/or the ADC block 104 when the gain settings in the PGA block 102 are changed. It would therefore be desirable to provide a technique that reduces the overall power in a data acquisition system when the gain settings of the PGA block 102 are modified.